Computers are known to include a central processing unit, system memory, a memory controller, video graphics circuitry, a chip set, and peripheral ports. The peripheral ports enable the central processing unit, and video graphics circuitry, to communicate data with peripheral devices such as monitors, printers, external memory, the Internet, etc.
As is known, the system memory space is divided into two sections, one for use by the central processing unit and the other section for use by peripheral devices via a peripheral bus. Such a peripheral bus may be a PCI bus or accelerated graphics port (AGP). In either case, a programmer may write code that utilizes these memory sections on behalf of central processing unit, the peripheral devices, and/or the video graphics processor.
To improve memory access, the central processing unit, and other peripheral devices, often use virtual addresses as opposed to physical addresses of the system memory. By using virtual addresses, processors can process code and/or data images that are larger than the memory size of the processors physical memory. To access the code and/or images from system memory, a virtual address is translated, via a translation technique, to a corresponding system memory address. Such a translation technique allows large code and/or images to be processed by processors with different amounts of physical memory, allows each application to be written as if the entire memory belonged to the processor, and allows a multiprocessing system to keep working sets for many programs simultaneously in system memory. While use of virtual addresses reduces circuit complexity, system memory cannot be accessed directly from a virtual address.
To convert a linear address into a physical address for system memory access in an X.86 implementation, paging is used. Paging, in an X86 implementation, produces a linear address by starting with a logical address (segment identifier and offset), and adding the segment base identified by the selector identifier to the segment offset. In essence, paging takes the linear address and uses a portion of the linear address to access a directory table. The retrieved information from the directory table is used to identify a paging table. Having identified the paging table, another portion of the linear address is used to identify a particular entry in the paging table. The retrieved entry from the paging table along with the remainder of the linear address produces the physical address of the system memory.
The retrieved entry from the paging table may be stored in a translation look aside table (TLB). As is known with the X.86 paging technique, the paging function may be enabled or disabled. When disabled, the TLB is not used. However, when the paging is enabled, a TLB entry is generated based on the linear address. In existing implementations of an X.86 processor, the paging function and TLB generation are performed utilizing a state machine. In other types of processors, such as the MIPS processor, software is used to process a portion of the TLB entry.
While existing paging techniques and system memory utilization function well in most applications, they are somewhat restricted in providing flexibility. For example, when an upgrade occurs, hardware typically needs to be replaced, as is the case with an X.86 processor. In addition, one type of processor, such an X.86 processor, generally does not interface with other types of processors, such an MIPS processor. For such processors to communicate, a conversion between an X.86 processing language and MIPS processing language needs to occur.
Therefore, a need exists for a method and apparatus that provides a more flexible utilization and addressing of system memory for processors within a computing system.